Circuitized substrates, such as those used in chip carrier electronic packages, have been and continue to be developed for many applications. Such a circuitized substrate typically comprises a plurality of conductive and organic dielectric layers laminated together to form a multilayered structure, with the upper layer designed for redistributing electrical signals from the chip mounted on the circuitized substrate through the substrate onto a larger circuitized area so that the circuitized substrate can properly interface with the hosting PCB having said larger area. An earlier version of chip carriers used ceramic as the dielectric rather than more recently developed organic materials of the type described in greater detail hereinbelow.
Generally speaking, there are two known types of such laminate organic chip carriers: those referred to as “wirebond” chip carriers; and those referred to as “C4” (for controlled collapse chip connection) chip carriers. In both, a chip is mounted on and electrically coupled to the carrier substrate's top side (upper) circuitry. In the case of a wirebond carrier, these connections are made using ultra thin aluminum or gold wires (called “wirebonds” by many) which are bonded at one end to chip contact sites on the chip's upper surface and at the other end to wirebond pads on the carrier substrate's upper surface circuitry. The chip is mounted on the underlying substrate preferably using a suitable adhesive. The carrier may then in turn be mounted on and electrically coupled to the PCB's upper surface circuitry using a plurality of solder balls which are mounted on pads on the PCB's upper surface and which form part of said circuitry. For “C4” chip carriers, the chip is coupled to the carrier substrate's circuitry using solder balls, the carrier having pads for having the solder balls secured thereto. An encapsulant material may be used to surround the solder balls in the array. The carrier's pads, like those of the PCB, in turn are coupled to the carrier's substrate internal circuitry which passes through the substrate to its undersurface, where solder balls are also used to coupled the substrate to the PCB (forming a ball grid array, or BGA final package). The present invention relates particularly to chip carriers of the wirebond type defined above in which the chip is wirebonded to the carrier substrate.
It is, of course, a key objective of all electronic package manufacturers to produce smaller and higher density packages which are still capable of increased capacity over previous structures. At least two concerns arise when attempting such miniaturization, particularly when considering that increased operational demands on such devices as semiconductor chips results in such chips operating at greater and greater temperatures. To prevent package breakdown as a result of possible chip failure, providing adequate, effective heat sinking for the chip is absolutely necessary. A second concern involves circuit density and particularly the ability to increase such density and yet provide effective connections between all of the conductors (substrate and chip) which form part of the package's electrical circuitry. The present invention, as defined herein, is particularly concerned with providing such effective heat removal from the chip, while substantially preventing chip separation (delamination) from the underlying organic laminate substrate by assuring an effective bond between chip and substrate. Significantly, the invention is able to do so while assuring a package with highly dense circuitry.
The following patents describe various types of known chip packages.
In U.S. Pat. No. 6,853,058, issued Feb. 8, 2005, there is described a semiconductor package having a semiconductor die “receiving member” configured to accept a semiconductor die in either the flip-chip or the wirebond orientations. First contact sites on a die receiving surface provide electrical connection with a flip-chip component. Second contact sites provide electrical connection with a wirebond component. Electrically conductive traces connect the first and second contact sites with terminal contact sites. The semiconductor package assembly may further include the flip-chip or wirebond component mounted over the die receiving surface. The assembly is further described as possibly including a mounting substrate in electrical connection with the terminal contact sites.
In U.S. Pat. No. 6,683,383, issued Feb. 27, 2004, there is described a wirebond structure which includes a copper pad formed on or in a surface of a microelectronic die (chip). A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350 degrees Celsius (C.).
In U.S. Pat. No. 6,522,015, issued Feb. 18, 2003, there is described a “micro-machine” package which includes a “micro-machine” chip having an area in a front surface of the chip. The package further includes a controller chip having a rear surface and a front surface. Bond pads are on the front surface of the controller chip. A bead secures the rear surface of the controller chip to the front surface of the micro-machine chip. By mounting the controller chip directly on the micro-machine chip, the size of the package is minimized. Further, the bead and controller chip form an enclosure around the micro-machine area. This enclosure protects the micro-machine area from the ambient environment.
In U.S. Pat. No. 6,124,546, issued Sep. 26, 2000, there is described a semiconductor integrated circuit chip package which includes top and bottom interposers, a semiconductor die attached to the top interposer, a wirebond or a flip-chip connector connected between the die and the top interposer, and a tab bond providing an electrical connection from the wirebond or the flip-chip connector to outside the bottom interposer.
In U.S. Pat. No. 6,077,766, issued Jun. 20, 2000, there is described an electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a BGA package to a substrate with attachment of the BGA package to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on opposite sides of a substrate.
In U.S. Pat. No. 5,616,958, issued Apr. 1, 1997, there is described an electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. The copper thermally conductive member provides heat sinking for the chip during operation. A high density circuit pattern is provided on the polyimide and is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density. The chip is coupled to the higher density portion of the circuitry which then may “fan out” to the lesser (and larger) density lines and/or pads of the other portion of the circuitry. The resulting package is also of a thin profile configuration and particularly adapted for being positioned on and electrically coupled to a PCB or the like substrate having conductors thereon.
In U.S. Pat. No. 5,463,250, issued Oct. 31, 1995, there is described a package for power semiconductor components which permits thermal dissipation and current conductance. The package includes a frame assembly bonded to a substrate on which a power semiconductor chip is mounted. The frame assembly has a wirebond grid for connecting short, uniform length wirebonds to the surface of the chip. The grid is configured so as to have a portion overlaying and spaced from the chip a distance less than a distance required to connect a wirebond of optimal length to each contact site of the chip. The package also uses an inner mounting pad on which the power semiconductor chip is directly mounted. The coefficient of thermal expansion of both the chip and the copper are described as being comparable. A ceramic “core” is located beneath the pad and includes a plurality of spaced copper “vias” which are described as being capable of restricting thermal expansion.
In U.S. Pat. No. 4,922,324, issued May 1, 1990, there is described a semiconductor integrated circuit device which includes a package base and a cavity formed with a ground electrode layer thereon. A semiconductor integrated circuit chip is provided on the ground electrode layer. De-coupling capacitors are provided on the surface of the cavity. A ground metal plate and outer leads are formed on the surface of the bottom of the package base. A metal connector is provided through the package base to connect, both electrically and thermally, the ground electrode layer and the ground metal plate.
In U.S. Pat. No. 4,705,917, issued Nov. 10, 1987, there is described a microelectronic package of the aforementioned, earlier ceramic type, designed for the protection, housing, cooling and interconnection of the microelectronic chip. The package is made of a plurality of ceramic layers, each of which carries a particular electrically conductive pattern and which have interior openings therein so as to provide recesses in which the chip and discrete capacitors can be located and connected.
As defined herein, the present invention provides for enhanced thermal sinking from the semiconductor chip in a package which utilizes organic dielectric materials as part of the laminated substrate while also providing an effective chip-substrate adhesive bond in such a manner so as to substantially prevent delamination of the chip from the substrate, e.g., during subsequent solder ball re-flow processing. It is believed that such an invention would represent a significant advancement in the art.